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20110 www.vishay.com 360 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors very fast infrared transceiver module (vfir, 16 mbit/s) irda ? serial interface compatible 2.7 v to 5.5 v supply voltage range description the tfdu8108 transceiver is part of a family of low power consumption infrared transceiver modules. it is compliant to the irda physic al layer standard for vfir infrared data communication, supporting irda speeds up to 16 mbit/s (vfir) and carrier based remote con- trol modes up to 2 mhz. integrated within the trans- ceiver module are a pin photodiode, an infrared emit- ter (ired), and a low-power control ic. at a minimum, a vcc bypass capacitor is the only external component required implementing a com- plete solution. for limiting the transceiver?s internal power dissipation one additional resistor might be necessary. the transceiver can be operated with logic i/o voltages as low as 1.8 v. features ? compliant to the latest irda physical layer standard (up to 16 mbit/s), hp-sir ? , sharp ask ? and tv remote control ? compliant to the irda "serial interface specification fo r transceivers" ? surface mount soldering to side and top view ori- entation ? surface mount package 9.7 x 4.7 x 4.0 mm 3 for side view and top view applications ? operating supply voltage from 2.7 v to 5.5 v ? compliant to all logic levels between 1.8 v and 5 v ? tv remote control support ? low power consumption (2 ma idle supply cur- rent) ? power shutdown mode (1 a shutdown current) ? tri-state-receiver output, weak pull-up when in output is disabled ? built - in emi protection - no external shielding necessary ? pin to pin compatible to legacy vishay sir and fir infrared transceivers ? eye safety class 1 (iec60825-1, ed. 2001), limited led on-time, led current is controlled, no single fault to be considered ? lead (pb)-free device ? qualified for lead (pb)-free and sn/pb processing (msl4) ? device in accordance with rohs 2002/95/ec and weee 2002/96/ec ? split power supply, can be driven by a separate power supply not loadin g the regulated supply. u.s. pat. no. 6,157,476 applications ? notebook computers, desktop pcs, palmtop computers (win ce, palm pc), pdas ? digital still and video cameras ? printers, fax machines, photocopiers, screen projectors ? mp3 players ? telecommunication products (cellular phones, pagers) ? internet tv boxes, video conferencing systems ? external infrared adapters (dongles) ? medical and industrial data collection devices package tfdu 8 10 8 ba b y face (uni v ersal) w eight 200 mg 19497 e3
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 361 ordering information functional block diagram v cc1 : analog supply voltage v logic : digital supply voltage, i/o reference voltage v cc2 : independent supply voltage for the led driver serial interface according the irda standard "serial interface for transceiver control" sclk: clock line as timing reference*) txd: tx/swdat - line*) rxd: rx/srdat - line*) *) see appendix a for definitions definitions: in the vishay transceiver data sh eets the following nomenclature is used for defining the irda operating modes: ? sir: 2.4 kbit/s to 115.2 kbit/s, equivalent to the ba- sic serial infrared st andard with the physical layer version irphy 1.0 ? mir: 576 kbit/s to 1152 kbit/s ? fir: 4 mbit/s ? vfir: 16 mbit/s mir and fir were implement with irphy 1.1, followed by irphy 1.2, adding the sir low power standard. irphy 1.3 extended the low power option to mir and fir and vfir was added with irphy 1.4. a new version of the standard in any case obsoletes the former ver- sion. pin description part number description qty / reel tfdu8108-tr3 oriented in carrier tape for side view surface mounting 1000 pcs TFDU8108-TT3 oriented in carrier tape for top view surface mounting 1000 pcs tfdu8108 in tube 50 pcs figure 1. functional block diagram 19493 agc v + - + asic sclk txd gnd serial interface voltage regulator v cc 1 v logic v cc 2 rxd driver + irkat logic gnd pin number function description i/o active 1 ired anode ired anode to be externally connected to v cc2 this pin is allowed to be supplied from an uncontroll ed power supply seperated from the controlled v cc1 - supply. 2 ired cathode ired cathode, internal ly connected to driver transistor 3 txd transmit data input, dynamically loaded i high 4 rxd received data output, tri-state cmos driver output capable of driving a standard cmos or ttl load. no external pull-up or pull- down resistor is requir ed. pin is current limit ed for protection against programming errors. the output is loaded with a weak 500 k pull- up, when in sd mode. the rxd echoes the optical txd signal duration transmission. olow 5 sclk serial clock, dynamically loaded i high 6v cc supply voltage 7v logic supply voltage for digital part, 1.8 v to 5.5 v, defines logic swing for txd, sclk, and rxd 8 gnd ground
www.vishay.com 362 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors babyface (universal) absolute maximum ratings reference point ground (pin 8) unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. due to the internal limitation measures the device is a "class1" device. it will not exceed the irda ? intensity limit of 500 mw/sr. figure 2. pinning "u" option babyface (universal) ired detector 1234567 8 170 8 7 parameter test conditions symbol min ty p. max unit supply voltage range, transceiver 0 v < v cc2 < 6 v v cc1 - 0.5 6 v supply voltage range, transmitter 0 v < v cc1 < 6 v v cc2 - 0.5 6 v supply voltage range, transceiver logic 0 v < v cc1 < 6 v v logic - 0.5 6 v ired anode voltage v ireda - 0.5 6 v transmitter data input voltage v txd - 0.5 v logic + 0.5 v receiver data output voltage v rxd - 0.5 v logic + 0.5 v input currents for all pins, except ired anode pin 10 ma output sinking current 25 ma power dissipation see derating curve, figure 7 p d 350 mw junction temperature t j 125 c ambient temperature range (operating) t amb 0+ 85c storage temperature range t stg - 40 + 100 c soldering temperature see recommended solder profile (see figures 4 to 6) 260 c average output current i ired (dc) 130 ma repetitive pulse output current < 90 s, t on < 20 % i ired (rp) 600 ma virtual source size met hod: (1 - 1/e) encircled energy d2.52.8 mm maximum intensity for class 1 operation of iec825-1 or en60825-1, edition jan. 2001 irda ? specified maximum limit internal limitation to class 1 500 mw/sr
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 363 electrical characteristics transceiver t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not gua ranteed nor subject to production testing. *) standard illuminant a. **) in shutdown condition the devic e is not ambient light sensitive. ***) the device will work with less tight levels than specified min/max values of the logic input voltage. it is recommended to use the speci- fied min/max values to minimize operating/standby supply currents. parameter test conditions symbol min ty p max unit supply voltage v cc1 v cc1 2.7 5.5 v supply voltage v logic v logic 1.8 5.5 v dynamic supply current receive mode only. in transmit mode, add the averaged programmed current of ired current as i cc2 dynamic supply current active, sir, e e = 0 klx (idle) t = - 25 c to 85 c i cc1 0.8 2.5 ma dynamic supply current active, vfir, e e = 0 klx, (idle) t = - 25 c to 85 c i cc1 10 ma dynamic supply current active, no load e e = 0 klx, (idle) t = - 25 c to 85 c i logic 5a dynamic supply current e e = 1 klx*) receive mode, e eo = 100 mw/m 2 (9.6 kbit/s to 4.0 mbit/s), r l = 10 k to v logic = 5 v, c l = 15 pf t = - 25 c to 85 c i logic 1ma standby supply current inactive, set to shutdown mode t = 25 c, e e = 0 klx t = 25 c, e e = 1 klx*) **) i sd 2 2 a a standby supply current shutdown mode, **) t = 85 c i sd 5a operating temperature range t a 0+ 85c output voltage low c load = 15 pf, v logic = 3 v, i olo < + 500 a v olo 0.4 v output voltage high c load = 15 pf, v logic = 5 v, i ohi < - 250 a v ohi 0.8 x v logic v input voltage high (txd, sclk) v il - 0.5 0.5 input voltage high (txd, sclk) v ih v logic - 0.3 6 v logic decision level (txd, sclk) ***) v il 0.5 x v logic v input leakage current (txd, sclk) i l - 10 + 10 a input capacitance c i 5pf
www.vishay.com 364 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors optoelectronic characteristics receiver t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. parameter test conditions symbol min ty p. max unit minimum detection threshold irradiance 9.6 kbit/s to 115.2 kbit/s, sir = 850 nm to 900 nm e e 25 40 mw/m 2 minimum detection threshold irradiance 1.152 mbit/s, mir = 850 nm to 900 nm e e 65 90 mw/m 2 minimum detection threshold irradiance 4 mbit/s, fir = 850 nm to 900 nm e e 85 90 mw/m 2 minimum detection threshold irradiance 16 mbit/s, vfir = 850 nm to 900 nm e e 160 200 mw/m 2 maximum detection threshold irradiance = 850 nm to 900 nm e e 510 kw/m 2 logic low receiver input irradiance e e 4 mw/m 2 rxd pulse width of output signal, 50 % sir mode input pulse length 20 s, 9.6 kbit/s t pw 1.3 2.6 s rxd pulse width of output signal, 50 % sir mode input pulse length 1.41 s, 115.2 kbit/s t pw 1.3 2.6 s rxd pulse width of output signal, 50 % mir mode input pulse length 217 ns, 1.152 mbit/s t pw 200 260 ns rxd pulse width of output signal, 50 % fir mode input pulse length 125 ns, 4 mbit/s t pw 105 125 145 ns rxd pulse width of output signal, 50 % fir mode input pulse length 250 ns, 4 mbit/s t pw 225 285 ns rxd pulse width of output signal, 50 % input pulse length 16 mbit/s, vfir 39.5 ns < p wopt < 43 ns t pw 32 42 52 ns rxd rise time of output signal 20 % to 80%, c l = 15 pf t r (rxd) 2 5 15 ns rxd fall time of output signal 20 % to 80%, c l = 15 pf t r (rxd) 2 5 15 ns rxd fall time of output signal 90 % to 10%, c l = 15 pf t r (rxd) 530ns rxd jitter, leading edge, sir mode input irradiance = 40 mw/m 2 , 115.2 kbit/s 350 ns rxd jitter, leading edge, mir mode input irradiance = 100 mw/m 2 , 1.152 mbit/s 40 ns rxd jitter, leading edge, fir mode input irradiance = 100 mw/m 2 , 4 mbit/s 20 ns rxd jitter, leading edge input irradiance = 200 mw/m 2 , 16 mbit/s, vfir mode 57ns rxd output pulse delay t rxddel 1s latency t lat 55 100 s receiver startup time t por 100 500 s
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 365 transmitter t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not gua ranteed nor subject to production testing. *) programmable using the"serial interf ace? programming sequence, see appendix a fo r implementation guidance and appendix b for in- tensity values and range. parameter test conditions symbol min ty p. max unit ired operating current internally controlled*) v cc1 = 3.3 v, the maximum current is limited internally. an external resistor can be used to reduce the power dissipation at higher operating voltages, see derating curve. i d 8 16 32 64 128 256 512 600 ma max. output radiant intensity v cc = 3.3 v, = 0,15 txd = high, r1 = 0 programmed to max. power level i e 0.3 mw/sr/ma output radiant intensity v cc = 5.0 v, = 0, 15 txd = low, programmed to shutdown mode i e 0.04 mw/sr txd pulse width of output signal, 50 % input pulse length 1.63 s, 115.2 kbit/s t pw 1.45 2.20 s txd pulse width of output signal, 50 % input pulse width 0.1 s < t txd < 60 s t pw t txd input pulse width t txd 60 s 20 60 s txd pulse width of output signal, 50 % input pulse length 250 ns, (fir, double pulse) t pw 240 260 ns txd pulse width of output signal, 50 % input pulse length 217.0 (mir) t pw 115 260 ns txd pulse width of output signal, 50 % fir mode input pulse length 125 ns (fir) t pw 115 125 135 ns txd pulse width of output signal, 50 % input pulse length 41.7 ns t pw 38.3 45.0 ns output radiant intensity, angle of half intensity 24 peak - emission wavelength p 870 900 nm spectral bandwidth 40 nm optical rise time, fall time t ropt , t fopt 19 ns optical overshoot 15 %
www.vishay.com 366 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors recommended circuit diagram operated with a low impedance power supply the tfdu8108 series devices need no external compo- nents. however, depending on the entire system design and board layout, additional components may be required (see figure 3). vishay transceivers integrate a sensitive receiver and a built-in power driver. the combination of both needs a careful circuit board layout. the use of thin, long, resistive and inductive wiring must be avoided. the inputs (txd, sclk) and the output rxd should be directly dc-coupled to the i/o circuit. r1 is used for reducing the power dissipation when operating the device at a supply voltage of v cc2 > 4 v. for increasing the max. output power of the ired, the value of the resistor should be reduced. it should be dimensioned to keep the ired anode voltage below 4 v for using the full temperature range. for device and eye protection the pulse duration and current are internally limited. r2, c1 and c2 are optional and dependent on the quality of the supply voltage v cc1 and injected noise. an unstable power supply with dropping voltage dur- ing transmission may reduce sensitivity (and trans- mission range) of the transceiver. the placement of these parts is critical. it is strongly recommended to position c2 as near as possible to the transceiver power supply pins. an electrolytic capacitor should be used for c1 while a ceramic capacitor is used for c2. recommended application circuit components i/o and software for operating the device from a controller i/o a driver software must be implemented. mode switching and programming the generic irda "serial interface programming" needs no special settings for the device. only the cur- rent control table must be taken into account. for the description see the appendix a, b and c and the irda document "serial interface specification for transceiv- ers" figure 3. recommended a pplication circuit all external components (r, c) are optional ired cathode ired anode rxd v cc g n d txd sclk v logic c2 c1 r2 r1 v cc2 rxd g n d v cc1 sclk txd v logic 170 8 9 component recommended value c1 4.7 f, 16 v c2 0.1 f, ceramic r1 recommended for v cc2 4 v depending on current limit r2 < 10 , 0.125 w
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 367 recommended solder profiles solder profile for sn/pb soldering lead (pb)-free, recommended solder profile the tfdu8108 is a lead (pb)-free transceiver and qualified for lead (pb)-free processing. for lead (pb)- free solder paste like sn (3.0 - 4.0) ag (0.5 - 0.9) cu, there are two standard reflow profiles: ramp-soak- spike (rss) and ramp-to-spike (rts). the ramp- soak-spike profile was developed primarily for reflow ovens heated by infrared radiation. with widespread use of forced convection reflow ovens the ramp-to- spike profile is used increas ingly. shown below in fig- ure 5 and 6 are vishay's recommended profiles for use with the tfdu8108 transceivers. for more details please refer to the application note ?smd assembly instructions? (http://www.vishay.com/docs/82602/82602.pdf). a ramp-up rate less than 0.9 c/s is not recom- mended. ramp-up rates faster than 1.3 c/s could damage an optical part because the thermal conduc- tivity is less than compared to a standard ic. wave soldering for tfduxxxx and tfbsxxxx transceiver devices wave soldering is not recommended. manual soldering manual soldering is the standard method for lab use. however, for a production process it cannot be rec- ommended because the risk of damage is highly dependent on the experience of the operator. never- theless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. storage the storage and drying processes for all vishay transceivers (tfduxxxx and tfbsxxx) are equiva- lent to msl4. the data for the drying procedure is given on labels on the packing and also in the application note "taping, labeling, storage and packing" (http://www.vishay.com/docs/82601/82601.pdf). current derating diagram figure 4. recommended solder profile for sn/pb soldering 0 20 40 60 8 0 100 120 140 160 1 8 0 200 220 240 260 0 50 100 150 200 250 300 350 time/s temperat u re (c) 2...4 c/s 2...4 c/s 10 s max. at 230 c 120 s...1 8 0 s 160 c max. 240 c max. 90 s max. 1 9535 figure 5. solder profile, rss recommendation figure 6. rts recommendation figure 7. current derating diagram 0 25 50 75 100 125 150 175 200 225 250 275 0 50 100 150 200 250 300 350 time/s temperat u re/c 30 s max. 2 c...3 c/s 2 c...4 c/s 90 s...120 s t 217 c for 70 s max t peak = 260 c 70 s max. t 255 c for 10 s....30 s 19532 0 20 40 60 8 0 100 120 140 160 1 8 0 200 220 240 260 2 8 0 0 50 100 150 200 250 300 time/s temperat u re/c < 4 c/s 1.3 c/s time a b o v e 217 c t 70 s time a b o v e 250 c t 40 s peak temperat u re t peak = 260 c < 2 c/s t peak = 260 c max 0 100 200 300 400 500 600 - 40 - 20 0 20 40 60 8 0 100 120 140 peak operating c u rrent (ma) temperat u re ( c) 14 8 75 c u rrent derating as a f u nction of the maxim u m for w ard c u rrent of ired. maxim u m d u ty cycle: 25 % .
www.vishay.com 368 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors tfdu8108 - babyface (universal) package (mechanical dimensions) figure 8. mechanical drawing, di mensions in mm, tolerance 0.2 mm if not otherwise shown 18473-1
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 369 recommended smd pad layout reel dimensions figure 9. mechanical drawing, di mensions in mm, tolerance 0.2 mm if not otherwise shown 7x1=7 8 1 1 16524-1 2.5 ( 2.0) 0.6 ( 0.7) figure 10. reel dimensions, dimens ions in mm, tolerance 0.2 mm tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 14017 dra w ing- n o.: 9. 8 00-5090.01-4 iss u e: 1; 29.11.05
www.vishay.com 370 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors tape dimensions drawing-no.: 9.700-5251.01-4 issue: 3; 02.09.05 19 8 22 figure 11. tape drawing,tfdu8108 for top view mounting, tolerance 0.1 mm
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 371 drawing-no.: 9.700-5297.01-4 issue: 1; 04.08.05 19 8 75 figure 12. tape drawing, tfdu8108 for side view mounting after mounting, tolerance 0.1 mm
www.vishay.com 372 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors tube drawing figure 13. tube drawing 19496
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 373 appendix a serial interface implementation basics of the ir da definitions the data lines are multip lexed with the transmitter and receiver signals and separate clocks are used since the transceivers respond to the same address. when no infrared communication is in progress and the serial bus is idle, the irtx line is kept low and irrx is kept high. functional description the serial interface is designed to interconnect two or more devices. one of the devices is always in control of the serial interface and is responsible for starting every transaction. this device functions as the bus master and is always the in frared controller. the infra- red transceivers act as bu s slaves and only respond to transactions initiated by the master. a bus transac- tion is made up of one or two phases. the first phase is the command phase and is present in every trans- action. the second phase is the response phase and is present only in those transactions in which data must be returned from the slave. if the operation involves a data transfer from the slave, there will be a response phase following the command phase in which the slave will output the data. the response phase, if present, must begin 4 clock cycles after the last bit of the command phase, as shown in figures 16 and 17, otherwise it is assumed that there will be no re sponse phase and the master can terminate the transaction. the sclk line is always driven by the master and is used to clock the data being written to or read from the slave. this line is driven by a totem-pole output buffer. the sclk line is always stopped when the serial interface is idle to minimize power consumption and to avoid any interference with the analog circuitry inside the slave. there are no gaps between the bytes in either the command or response phase. data is always transferred in little endian order (least significant bit first). input data is sampled on the rising edge of sclk. irtx/swdat output data from the controller is clocked by sclk fallin g edge. irrx/srdat output data from the slave is clocked by sclk rising edge. each byte of data in both command and response phases is preceded by one start bit. the data to be written to the slave is carried on the irtx/swdat line. when the control interfac e is idle, this line carries the infrared data signal used to drive the transmitter led. when the first low-to-high transition on sclk is detected at the beginning of the command sequence, the slave will disable the tr ansmitter led. when the first low-to-high transition on sclk is detected at the beginning of the command sequence, the slave will disable the transmitter led. the infrared controller then outputs the command string on the irtx/ swdat line. on the last sclk cycle of the command sequence the slave re-enables the transmitter led and normal infrared transmission can resume. no transition on sclk must occur until the next com- mand sequence otherwise the slave will disable the transmitter led again. read data is carried on the irrx/srdat line. the slave disables the internal sig- nal from the receiver photo diode during the response phase of a read tr ansaction. the addressed slave will output the read data on the irrx/srdat line regard- less of the setting of the receiver output enable bit in the main control register (main-ctrl-0). non addressed slaves will tri-state the irrx/srdat line. when the transceiver is powered up, the irtx/swdat line should be kept low and sclk should be cycled at least 30 times by the infrared controller before the first command is issued on the irtx/swdat line, see fig- ure 18. this guarantees that the transceiver interface circuitry will properly initia lize and be ready to receive commands from the controller. in case of a multiple transceiver configuration, only one transceiver should have the receiver output enabled. figure 14. interface to two infrared transceivers figure 15. infrared dongle with differential signaling v cc optical transcei v er ofe a tx/s w dat rx/srdat sclk optical transcei v er ofe b tx/s w dat rx/srdat sclk irtx/s w dat irrx/srdat sclk1 sclk2 infrared controller 17092 17093 tx/s w dat rx/srdat sclk a_sl g n d g n d v cc shielded ca b le connector g n d v cc infrared controller irtx+/s w dat+ irtx-/s w dat- irrx+/srdat+ irrx-/srdat- sclk+ sclk- l v ds transcei v er optical transcei v er
www.vishay.com 374 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors a series resistor (approx. 200 ) should be placed on the receiver output from each transceiver to prevent large currents in case a conflict occurs due to a pro- gramming error. note: generally the abbreviati ons irtx/irrx and txd/rxd are used for the data transmission li nes for the optical communication. irtx/irrx is mostly used at the controller, txd/rxd at the trans- ceiver note: if the apen bit in control regist er 0 is set to 1, the internal sig- nal from the receiver photo di ode is disconnected and the irrx/ srdat line is pulsed low for one cl ock cycle at the end of a write or special command. note: during a read transaction t he infrared controller sets the irtx/swdat line high after s ending the address and index byte (or bytes). it will then set it low two clock cycles before the end of the transaction. it is strongly re commended that optical transceiv- ers monitor this line instead of counting clock cycles in order to detect the end of the read transaction. this will always guarantee correct operation in case two or more transceivers from different manufacturers are shari ng the serial interface. figure 16. special command waveform figure 17. write data waveform figure 18. initial reset timing sclk irtx/ s w dat irrx/ srdat start address & co n trol 19502 19503 sclk irtx/ swdat irrx/ srdat start address,index, dir. start data 19504 sclk irtx/ swdat irrx/ srdat > 30 clock cycles figure 19. write data waveform with extended index figure 20. read data waveform figure 21. read data waveform with extended index 19505 19506 19507
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 375 switching characteristics maximum capacitive load = 20 pf *) *) maximum capacitive load = 20 pf. that is is different from "serial interface - specif ication". for the bus protocol see "recom mended serial interface for transceiver control, draft version 1.0a, march 29, 2000, irda". in a ppendix b the transceiver related data are given. symbol parameters test conditions min. max. unit t ckp sclk clock period rising edge of sclk to next rising edge of sclk 250 infinity ns t ckh sclk clock high time at 2.0 v for single-ended signals 60 ns t cki sclk clock low time at 0.8 v for single-ended signals 80 ns t dotv output data valid (from infrared controller) after falling edge of sclk 40 ns t doth output data hold (from infrared controller) after falling edge of sclk 0 ns t dorv output data valid (from optical transceiver) after rising edge of sclk 40 ns t dorh output data hold (from optical transceiver) after rising edge of sclk 40 ns t dorf line float delay after rising edge of sclk 60 ns t dis input data setup before rising edge of sclk 10 ns t dih input data hold after rising edge of sclk 5 ns
www.vishay.com 376 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors appendix b application guideline in the following some guide line is given for handling the tfdu8108 in an application ambient, especially for testing. it is also a gu ideline for inte rfacing with a controller. we recommend to use for first evaluation the vishay irm1802 controller. for more information see the special data sheet. driver software is avail- able on request. contact irdc@vishay.com. serial interface c apability of the vishay irda transceivers abstract a serial interface allows an infrared controller to com- municate with one or more infrared transceivers. the basic specification of the irda specified interface is described in "serial interface for transceiver control, v 1.0a", irda. this part of the document describes the capabilities of the serial interface implemented in the vishay irda transceivers tfdu8108. the vfir (16 mbit/s) device tfdu8108 and the fir device tfdu6108 (4 mbit/s) are using the same interface specification (with spe- cific identification and programming). irda serial interface basics the "serial interface for tr ansceiver control" is a master/slave synchronous se rial bus, which uses the txd and rxd as data lines and the sclk as clock line with a minimum period of 250 ns. the transceiver works always as slave and jumps into a control mode on the first rising edge of the clock line remaining there until the command phase is finished. after power-on, it is required to initialize the transceiver by at least 30 clock cycles of sclk with txd continu- ously low before starting programming. if txd gets active (high) during the initialization period the initialization must be repeated. a data word consists of one byte preceded by one start bit. the specified serial interf ace allows the communica- tion between infrared controller and transceiver through write and read transactions. in two register blocks with different functions all data is stored for operating the interface. the main control registers allow write and read transactions and here the exe- cutable configuration of the device is stored. the extended indexed registers contain the description of the supported functionality of the device and can be read only. power-on after power on the transceiver is in the default mode shown in table b1. addressing the transceiver is addressable by three address bits. there are individual and common addresses with the values shown in table b2. registers data depth in general data registers use a data depth of eight bits. sometimes it is not necessary to implement the full depth. in such cases the invisible bits are consid- ered as a zero. registers the register content is listed in the tables b4 to b7. data acknowledgment data acknowledgement generated by the slave is available if the apen bit is set to 1 in the common control register, see the "main_ctrl_0" register values table b4. in irda default state this functionality is dis- abled. it is recommended to enable this function. table b1: power-on default mode function tfdu8108 power mode (active or sleep) sleep rxd (receive) disable (floating tri-state) txd_led (emitter driver): disable apen (acknowledgment) disable infrared operating mode (speed) sir transmitter power (intensity setting) max. sir power level
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 377 table b2: addressing table b3: index commands note: the main_ctrl_1 register is written software dependent on t he offset value stored in ext_ctrl_7 and ext_ctrl_8 registers. the main_ctrl_1 register can be set to t he following values, shown in the table. tables b4 to b7: control register values the status of the entire transceiver is stored in the control registers. table b4: register main-ctrl-0 command structure: c is the transf er direction: ? c = 1: write or reset transaction ? c = 0: read transaction main-ctrl-0, register values *) apen - acknowledge pulse enable, (optional) this bit is used to enable the acknowledge pulse. when it is se t to 1 and rx oen is 1 (receiver output enabled) the irrx/srdat line will be set low for one clock cycle upon successful completion of every write command or s pecial command with individual (non broadc ast) transceiver address. the inte rnal signal from the receiver photo diode is disconnected when this bit is set to 1. description address value addr [2:0] individual address 010 common (broadcast) address 111 commands index [3:0] mode write/read actions register name data bits data tfdu8108 default 0h w/r common control main-ctrl-0 register [4:0] 00h 1h w/r infrared mode main-ctrl-1 register [7:0] 00h 2h w/r txd power level main-ctrl-2 register [7:4] 70h 3h - bh x not used ch x not used dh w reset transceiver, only one byte! r not used eh x not used fh w not used r extended indexing c 0 0 0 0 bit 0 bit 1 bit 2 1 bit 0 bit 1 bit 2 0 bit 4 0 0 0 index [3:0], 0h addr [0:2] data [7:0] value function default bit 0 pm sl - power mode select low power-mode (shutdown (sleep) mode) normal operation power mode shutdown bit 1 rx oen - receiver output enable irrx/srdat line disable (tristated) irrx/srdat line enabled disabled bit 2 tled en - transmitter led enable disabled enabled disabled bit 3 not used not used bit 4 apen *) don?t acknowledge acknowledge disabled
www.vishay.com 378 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors table b5: register main-ctrl-1 command structure: main-ctrl-1, register values depending on the values of "ext_ctrl_7" and "ext_ctrl_8" check for correct main_ctrl_1. in case of an error, the transceiver wi ll load 00h into the main_ctrl_1 register and will not give an acknowledgement. table b6: register main-ctrl-2 command structure: main-ctrl-2, data [7 :0], bit 4 to bit 7 *) device is tested under this c ondition. default setting is 7xh. c 1 0 0 0 bit 0 bit 1 bit 2 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 index [3:0], 1h addr [0:2] data [7:0] data [7:0] function 00h sir (default) 01h mir 02h fir 03h apple talk ? (fir functionality) 05h vfir - 16 08h sharp ir ? (sir functionality) 20h irda cir c 1 0 0 bit 0 bit 1 bit 2 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 index [3:0], 1h addr [0:2] data [7:0] data [7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txd - ired [ma] le [mw/sr] 15 (typ. on axis) link distance on axis recommended for 8xh- fxh 1xxxxxxx 512 140 ( 240) vfir > 0.7 m, fir > 1 m (link distance limited by receiver sensitivity) vfir/fir standard 7xh *) 0111xxxx 256 > 70 (120) *) sir >1 m fir > 0.7 m, vfir > 0.5 m sir, more ext. fir lp 6xh0110 128 35 (60) sir > 0.70 m fir > 0.50 m vfir > 0.30 m extended fir low power 5xh0101 64 16 (30) sir > 0.5 m fir > 0.30 m vfir > 0.30 m vfir low power/ fir low power 4xh0100 (48) 3xh0011 32 8 (19) sir > 0.35 m fir > 0.20 m vfir > 0.20 m sir low power 2xh0010 16 40 (10) sir low power, min without optical windows 1xh0001 8 (5) sir > 0.15 m fir > 0.10 m vfir > 0.10 m close distance, e.g. docking station 0xh0000xxxx 0 0
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 379 note: calculated expected range in dependence of ired drive current for the case that the receiver sensitivity is not limiting the range, on axis, for information only. note: calculated expected range in dependence of ired drive current for the case that t he receiver sensitivity is not limiting the range; 15 off-axis, for information only. table b7: reading exte nded indexed registers note: read data with extended index e_indx is one of the extended indexed registers. it must be addressed via a precursor of w riting all 1s into the normal index location, thus index[3:0] = fh. it is an 8 bit address value, which must be followed by 3 sclk cy cles plus a start clock before reading the data value. as in the normal read transaction, the in put signal, txd, must be set one clock cyc le on low (master ready to receive) and then on high for the next 3 sclks and continuing through the entire response phase. the correspo nding reaction of the rxd line and the 8 bit data value is then read out as depicted below, noting that the read data value comes aft er the 3 sclk cycles. read command structure: response: extended indexed registers ired current i f [ma] intensity i e [mw/sr] d[m] at e e = 100 mw/m 2 d[m] at e e = 40 mw/m 2 d[m] at e e = 90 mw/m 2 d[m] at e e = 225 mw/m 2 512 240 1.55 2.45 1.63 1.03 256 120 1.10 1.73 1.15 0.73 128 60 0.77 1.22 0.82 0.52 64 30 0.55 0.87 0.58 0.37 48 22.50.470.750.500.32 32 15 0.39 0.61 0.41 0.26 16 7.5 0.27 0.43 0.29 0.18 8 3.75 0.19 0.31 0.20 0.13 ired current i f [ma] intensity i e [mw/sr] d[m] at e e = 100 mw/m 2 d[m] at e e = 40 mw/m 2 d[m] at e e = 90 mw/m 2 d[m] at e e = 225 mw/m 2 512 140.0 1.18 1.87 1.25 0.79 256 70.00.150.231.160.10 128 35.00.590.940.620.39 64 17.50.420.660.440.28 48 13.10.360.570.380.24 32 8.8 0.30 0.47 0.31 0.20 16 4.4 0.21 0.33 0.22 0.14 8 2.2 0.15 0.23 0.16 0.10 0 1 1 1 1 bit 0 bit 1 bit 2 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 c index [3:0], fh addr [0:2] e_index [0:7] bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data [0:7] action e_index [7:0] register name data [7:0] in tfdu8108 definition default in the tfdu8108 manufacture id 00h ext_ctrl_0 0bh chip information (factory reserved) read support, device id 01h ext_ctrl_1 c6h device id receiver recovery time power on stabilization 04h ext_ctrl_4 23h 100 s to 500 s receiver stabilization 05h ext_ctrl_5 30h 0
www.vishay.com 380 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors invalid commands handling commands and register addresses, which cannot be encoded by the serial interface, are ignored by the internal logic as invalid data. below the different types invalid command handling and the slave reaction is shown. reset two ways to set the serial interface into a defined state are available: the brute force method is to switch the power off and on and let the device recover in the default state. the software method is to set the irtx/swdat line low for 30 clock cycles of the clock line. if this line is detected as low for 30 clock cycles the transceiver is set into the command start state and all registers are set to the as default imple- mented values. table b8: invalid commands handling no reaction means that the slave does not start the respond phase. c is the transfer direction: ? c = 1: write or reset transaction ? c = 0: read transaction sclk max. frequency (4mhz) 4 mhz common capabilities 06h ext_ctrl_6 03h low power mode and programmable transmitter power supported supported infrared modes 07h ext_ctrl_7 2fh all listed in receive mode supported infrared modes 08h ext_ctrl_8 01h sharp ir mask id: released ver. set, followed by revision letter f0h ext_ctrl_240 0ah chip information (factory reserved) action e_index [7:0] register name data [7:0] in tfdu8108 definition default in the tfdu8108 description master command slave reaction on rxd/srdat invalid command in read mode index [3:0] & c = 0 no reaction invalid command in write mode index [3:0] & c = 1 no acknowledgement generating independent of the value of apen valid command in invalid read mode index [3:0] & c = 0 no reaction valid command in invalid write mode index [3:0] & c = 1 no acknowledgement generating independent of the value of apen valid command in valid write mode and invalid data index [3:0] & c = 1 no acknowledgement generating independent of the value of apen broadcast address in read mode addr [2:0] = 111 & c = 0 no reaction
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 381 appendix c serial interface programming guide the serial interface port of tfdu8108 enables an interface controller to communicate using a standard- ized protocol, recall module id and capability informa- tion, and implement receiver bandwidth mode swit- ching, led power control, shutdown and some other functions. this interface requires three signal lines: a clock line (sclk) that is used for timing, and two unidirectional lines multiplexed with the transmitter (txd, write) and receiver (rxd, read) signal lines. programming sequence formats supported are ? one-byte special commands ? two-byte write commands ? two-byte read commands ? three-byte read commands one-byte special command sequences are reserved for time-critical actions, while the two-byte write com- mand is predominantly used to set basic transceiver characteristics. more information can be found in the irda document "serial interface for transceiver con- trol, v 1.0a" on http://www.irda.org. serial interface timing specifications in general, serial interface programming sequences are similar to any clocked-data protocol: ? there is a range of acceptable clock rates, mea- sured from rising edge to rising edge ? there is a minimum data setup time before clock rising edges ? there is a minimum data hold time after clock rising edges recommended programming timing: ?f sclk < 8 mhz (according to the serial interface standard, quasi-static programming is possible) ?t sclk > 125 ns, ?t setup > 10 ns, ?t hold > 10 ns the timing diagrams, see figure 22, show the setup and hold time for the serial interface programming sequences. protocol specifications the serial interface protocol is a command-based communication standard and allows for the communi- cation between controller and transceiver by way of serial programming sequences on the clock (sclk), transmit (txd), and receive (rxd) lines. the sclk line is used as a clocking signal and the transmit/ receive lines are used to write/read data information. the protocol requires all transceivers to implement the write commands, but does not require the read- portion of the protocol to be implemented (though all transceivers must at least follow the various com- mands, even if they perform no internal action as a result). this serial interface follows but does not sup- port all read/ write commands or extended com- mands, supporting only the special commands and basic write/read commands. write commands to the transceiver take place on the sclk and txd lines and may use the rxd line for acknowledgment. a command may be directed to a single transceiver on the sclk, txd and rxd bus by specifying a unique three-bit transceiver address, or a command may be directed to all transceivers on the bus by way of a spe- cial three-bit broadcast address code. the vishay vfir transceiver tfdu8108 will respond to trans- ceiver address 010 and the broadcast address 111 only; it ignores all other transceiver addresses. all commands have a common "header" or series of leading bits, which take the form shown below. first bit sent to transceiver last bit sent to transceiver. the bits shown are placed on the txd (data) line and clocked into the transceiver using the rising edge of the sclk signal. only the data bits are shown as it is assumed that a clock is always present, and that the transceiver samples the data on the rising edge of each clock pulse. note: as illustrated in the diagram above, the protocol uses "little endian" ordering of bits, so that the lsb is sent first, and the msb is sent last for register addres ses, transceiver addresses, and read/ write data bytes. the notation t hat follows presents all addresses and data in lsb-to-msb order (bits 0, 1, 2, 3, ... 7) unless otherwise stated. figure 22. programming sequence 0 1 0/1 i0 i1 i2 i3 a0 a1 a2 ... ... sync. bits r/w 0/1 commands index transceiver address sclk tx 125 ns < tclk s tset u p > 10 ns thold > 10 ns 1 8 496
www.vishay.com 382 document number 82558 rev. 1.8, 16-mar-07 tfdu8108 vishay semiconductors one-byte special commands one-byte special commands are used for time-critical transceiver commands, such as full transceiver reset. a total of six special commands are possible, al- though only one command is available on the tfdu8108. two-byte write commands two-byte write commands are used for setting the contents of transceiver registers which control trans- ceiver such as shutdown/enable, receiver mode, led power level, etc. the register space requires four reg- ister address bits (index), although three codes are used for controlling the tran sceiver (see above). the 1111 escape code is for extended commands. the 3- bit transceiver address (a ddr) is for selecting the destination, e.g. 010 to tfdu8108 and 001 to tfdu6108. the second byte is data field (data) for setting the characteristics of the transceiver module, e.g. sir mode (00) or vfir (05) when the register address is 0001. the basic two-byte write command is illustrated below: some important serial interface programming sequences are shown in table c1. table c1: serial inte rface programming sequences 0 1 1 i0 i1 i2 i3 a0 a1 a2 0 0 sync. bits w special command code tr a n s c e i ve r address stop bits command programming sequence (binary) reset (set all registers to default value) 011 1011 010 00 0 1 1 i0 i1 i2 i3 a0 a1 a2 a3 d0..07 0 0 sync. bits w commands index transceiver address 8 data bits stop bits command tfdu8108 programming sequence (transceiver address: 010) common ctrl main_ctrl_0 data sync/c/index/addr/1/data/stop normal (enable all) 0fh 01 1 0000 010 1 11110000 00 shutdown 00h 01 1 0000 010 1 00000000 00 receiver mode main_ctrl_1 data sir 00h 01 1 1000 010 1 00000000 00 mir 01h 01 1 1000 010 1 10000000 00 fir 02h 01 1 1000 010 1 01000000 00 apple talk 03h 01 1 1000 010 1 11000000 00 vfir 05h 01 1 1000 010 1 10100000 00 sharp-ir 08h 01 1 1000 010 1 00010000 00 led intensity main_ctrl_2 data 8 ma 1xh 01 1 0100 010 1 00001000 00 16 ma 2xh 01 1 0100 010 1 00000100 00 32 ma 3xh 01 1 0100 010 1 00001100 00 64 ma 5xh 01 1 0100 010 1 00001010 00 128 ma 6xh 01 1 0100 010 1 00000110 00 256 ma 7xh 01 1 0100 010 1 00001110 00 512 ma fxh 01 1 0100 010 1 00001111 00
tfdu8108 document number 82558 rev. 1.8, 16-mar-07 vishay semiconductors www.vishay.com 383 ozone depleting subst ances policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releas es of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operat ing parameters must be validated for each customer application by the customer. should the buyer use vish ay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vis hay semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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